Um...uh...
Wow!Looks useful!And simple!
It'll be the fetch-decode-execute loop in my cpu model!(if you dont know what i mean,Lag circuit)
Divide the clock into nine "hours".
hour 1:IAR->RAM->IR,IR open
hour 2:IR close,close links
hour 3:first 6 digits of IR->RAM->RA,RA open,IAR->RAI
hour 4:RA close,close links
hour 5:middle 6 digits of IR->RAM->RB,RB open
hour 6:RB close,close links
hour 7:RA->SUB,RB->SUB,SUB->RC,SUB->RN,RC open,RN open,SUB->RAM,first 6 digits of IR->RAM,RAM open
hour 8:RC close,RN close,RAM close,close links,RA open,RB open,RN->MUX->0.(RAI->ADD,000001->ADD,ADD->IAR,IAR open)1.(RC->IAR,IAR open)
hour 9:IAR close,close links
(needs registers:6 bit registers a,b,c,ir,iar,1 bit registers(effectively just a d latch)n,18*64 ram ram)
(yeah yeah 2/3 of the time just fetching things cuz we dont have parell RAMs so we cant do the three fetch instructions at once 
)
(translated to human language is:
fetch instruction
fetch a
fetch b
calculate a-b,result go to c,negativeness go to n,write result to ram
if n then set instruction address to c else add 1 to instruction address register and put back
)
Well you should use Two's complement to do negative numbers instead of one's!
Also you should fix the length of the RAM and make the instruction length 3*log(ram size)